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| NB3N508S 3.3V, 216 MHz PureEdge VCXO Clock Generator with M-LVDS Output Description The NB3N508S is a high precision, low phase noise Voltage Controlled Crystal Oscillator (VCXO) and phase lock loop (PLL) that generates 216 MHz M-LVDS output from a 27 MHz crystal. The 100 ppm output pullable range is obtained using the VIN pin of the VCXO with usable range from 0 V to 3.3 V. The VCXO input pin VIN is a high-impedance input that can be driven directly from a pulse width modulated RC integrator circuit. The NB3N508S is designed primarily for data and clock recovery applications within end products such as ADSL modems, set-top box receivers, and telecom systems. This device is housed in 5.0 mm x 4.4 mm narrow body TSSOP-16 pin package. Features http://onsemi.com MARKING DIAGRAM 16 1 TSSOP-16 DT SUFFIX CASE 948F 1 16 NB3N 508S ALYWG G * * * * * * * * * * PureEdge Clock Family Provides Accuracy and Precision Performs Precision Clock Multiplication from 27 MHz Crystal Uses 27 MHz Fundamental Mode Crystal External Loop Filter is Not Required 216 MHz M-LVDS Output VCXO with Pull Range $100 ppm 0 V to 3.3 V VCXO Tuning Voltage Range Capabilities Phase Noise: Offset Noise Power 100 Hz -80 dBc 1 kHz -88 dBc 10 kHz -105 dBc 100 kHz -106 dBc 1 MHz -120 dBc 10 MHz -145 dBc Operating Range 3.3 V $5% These are Pb-Free Devices* A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. (c) Semiconductor Components Industries, LLC, 2006 October, 2006 - Rev. 0 1 Publication Order Number: NB3N508S/D NB3N508S VDD X1 27 MHz Crystal X2 VIN BN VCXO CLK Phase Detector Charge Pump VCO M-LVDS Output CLK GND Figure 1. NB3N508S Simplified Logic Diagram *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 2 NB3N508S X1 VDD VDD VDD VIN GND GND GND 1 2 3 4 5 6 7 8 16 15 14 13 X2 NC CLK CLK GND NC VDD NC NB3N508S 12 11 10 9 Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin 1 2, 3, 4, 10 5 6, 7, 8, 12 9, 11, 15 13 14 16 Name X1 VDD VIN GND NC CLK CLK X2 I/O Crystal Input Power Supply Input Power Supply - M-LVDS Output M-LVDS Output Crystal Input Description Crystal input(IN). Connect to a 27 MHz crystal. Positive power supply voltage. Analog voltage input pin that controls output oscillation frequencies. VIN pin range is from 0 V to 3.3 V. VIN voltage should not exceed VDD. Ground 0 V. These pins provide GND return path for the devices. No Connect. Inverted clock output. Typically loaded with 50 W receiver termination resistor across diff. pair. Noninverted clock output. Typically loaded with 50 W receiver termination resistor across diff. pair. Crystal input(OUT). Connect to a 27 MHz crystal. Recommended Crystal Parameters Crystal Fundamental AT-Cut Frequency Load Capacitance Shunt Capacitance, C0 Max Equivalent Series Resistance Max Initial Accuracy at 25C Temperature Stability Aging C0/C1 Ration 27 MHz 14 pF 7 pF 35 W 20 ppm 30 ppm 20 ppm 250 Max http://onsemi.com 3 NB3N508S Table 2. ATTRIBUTES Characteristics ESD Protection Human Body Model Machine Model Value > 4 kV > 400 V Level 3 UL 94 V-0 @ 0.125 in 6000 Devices Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) TSSOP-16 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 Table 3. MAXIMUM RATINGS Symbol VDD VI IOUT TA TSTG qJA qJA TSOL Parameter Positive Power Supply Input Voltage (VIN) M-LVDS Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb-Free 0 lfpm 500 lfpm (Note 2) TSSOP-16 TSSOP-16 TSSOP-16 Condition 1 GND = 0 V GND = 0 V Continuous Surge GND v VI v VDD Condition 2 Rating 4.6 VDD 25 50 0 to +70 -65 to +150 138 108 33 to 36 265 Unit V V mA mA C C C/W C/W C/W C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. JEDEC standard multilayer board - 2S2P (2 Signal, 2 Power). Table 4. DC CHARACTERISTICS (VDD = 3.135 V to 3.465 V, GND = 0 V, TA = 0C to +70C) Symbol IDD VIA VOD DVOD VOS DVOS VOH VOL ISC Characteristic Power Supply Current (outputs loaded with RL = 50 W) VCXO Control Voltage, VIN Differential Output Voltage (Note 3) Change in Magnitude of VOD for Complementary Output States (Notes 3, 6) Offset Voltage (See Figure 4) Change in Magnitude of VOS for Complementary Output States (Note 6) Output HIGH Voltage (Note 4) Output LOW Voltage (Note 5) Output Short Circuit Current CLK or CLK to GND -25 Min 42 0 480 -50 300 -50 1300 700 43 565 Typ 52 Max 62 3.3 650 50 2100 50 2425 Unit mA V mV mV mV mV mV mV mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. M-LVDS outputs require 50 W receiver termination resistor between differential. pair. See Figure 3 4. VOHmax = VOSmax + 1/2 VODmax. 5. VOLmax = VOSmin - 1/2 VODmax. 6. Parameters guaranteed by design but not tested in production. http://onsemi.com 4 NB3N508S Table 5. AC CHARACTERISTICS (VDD = 3.135 V to 3.465 V, GND = 0 V, TA = 0C to +70C, Note 7) Symbol fCLKIN fCLKOUT FNOISE Crystal Input Frequency Output Clock Frequency Phase-Noise Performance fCLKOUT = 216 MHz @ 100 Hz Offset from Carrier @ 1 kHz Offset from Carrier @ 10 kHz Offset from Carrier @ 100 kHz Offset from Carrier @ 1 MHz Offset from Carrier @ 10 MHz Offset from Carrier Spurious Noise Components FP tDUTY_CYCLE tR tF Crystal Pullability 0 V v VIN v 3.3 V Output Clock Duty Cycle (Measured at Crosspoint) Output Rise Time (CLK/CLK) (Note 8) Output Fall Time (CLK/CLK) (Note 8) "100 45 50 380 380 55 500 500 Characteristic Min Typ 27 216 -80 -88 -105 -106 -120 -145 -60 Max Unit MHz MHz dBc/Hz dBc/Hz ppm % ps ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. CLK/CLK loaded with 50 W receiver termination resistor between diff. pair. 8. Measured differentially (CLK - CLK) at 10% to 90%; RL = 50 W. Phase Noise 10.00dB/Ref -20.00dBc/Hz NOISE POWER (dBc) OFFSET FREQUENCY (Hz) Figure 3. Typical Phase Noise Plot (VDD = 3.3 V, VIN = 0 V; Room Temperature) http://onsemi.com 5 NB3N508S 200 216.06 Maximum 216.04 FREQUENCY ERROR (ppm) 150 100 50 0 -50 -100 -150 -200 -250 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Minimum FREQUENCY (MHz) 216.02 216 0 25 215.98 70 215.96 215.94 0 0.5 1.0 1.5 2.0 2.5 3.0 3.15 3.3 3.45 VIN, CONTROL VOLTAGE (V) VIN, CONTROL VOLTAGE (V) Figure 4. VCXO Pulling Range Figure 5. Output Clock Frequency vs. VIN and Temperature Figure 6. Typical Crystal Startup Time with VIN = 0 V at Ambient Temperature (1.99 ms) Figure 7. Typical Crystal Startup Time with VIN = 3.3 V at Ambient Temperature (694 ms) M-LVDS Driver Device CLK Zo = 50 W 50 W D M-LVDS Receiver Device CLK Zo = 50 W D Figure 8. Typical Termination for Output Driver and Device Evaluation CLK VOS CLK VOD VOH VOL Figure 9. H-LVDS Output http://onsemi.com 6 NB3N508S ORDERING INFORMATION Device NB3N508SDTG NB3N508SDTR2G Package TSSOP-16 (Pb-Free) TSSOP-16 (Pb-Free) Shipping 96 Units / Rail 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 NB3N508S PACKAGE DIMENSIONS TSSOP-16 CASE 948F-01 ISSUE A 16X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K K1 16 9 2X L/2 J1 B -U- L PIN 1 IDENT. 1 8 J N 0.15 (0.006) T U S 0.25 (0.010) M A -V- N F DETAIL E C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 8 EEE CCC EEE CCC SECTION N-N -W- NB3N508S/D |
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